1. Field of the Invention
The present invention relates to a large memory capacity semiconductor random access memory (RAM) device.
2. Description of the Prior Art
Recent progress of the semiconductor technology has made it possible to manufacture large memory capacity IC devices such as 1 M-bit dynamic RAMs, 4 M-bit dynamic RAMs and the like.
A semiconductor RAM IC has been generally constructed so as to perform its read/write operation with the input/output data having the same number of bits.
Generally, the memory functional test has been performed by sequentially reading out 1-bit information units from each memory cell of an internal memory matrix.
However, with an increase in the memory capacity of a memory IC device, a large amount of test time has been required to test the condition of all of the memory cells in the memory matrix. This problem is particularly significant in a large capacity memory in a 1-bit configuration comprising a pair of input and output data units.
The minimum test time Tmin (write time+read time) which is needed to test the conditions of all of the memory cells by reading out bit information units from each memory cell of a memory cell matrix one bit at a time is given by the following formula: EQU T.sub.1 =(Tw+Tr)*N*n (1)
where Tw is a write time needed for a 1-bit information unit, Tr is a read time needed for a 1-bit information unit, N is the number of bits and n is the number of test patterns.
As seen from the formula (1), the test time increases in proportion to the memory capacity (in terms of the number of bits).
The N.sup.3/2 or N.sup.2 testing method which takes into account effects to the peripheral memory cells about a memory cell to be tested is commonly performed but it requires a longer test time.
In order to shorten the test time of large capacity memory devices, a memory configuration is known which comprises a plurality of pairs of output data terminals and a pair of input data terminals, and can read out a 1-bit memory cell information unit as a memory cell information unit in a multi-bit form by means of a control signal. This memory configuration, for example, is described in detail in the paper titled "MEGABIT DRAM S" in the ISSCC 85 DIGEST OF THE TECHNICAL PAPERS, pages 288, 239 and 352.
In such a memory circuit arrangement which, for example, can read out 4-bit information units at the same time, the minimum test time T.sub.2 is as follows: EQU T.sub.2 =(Tw+1/4Tr)*N*n (2)
As a result, the read time T.sub.r is reduced by a factor of 4 so as to provide an improved test time.
However, the prior art memory circuit arrangement is not able to decrease the writing time for 1-bit data units in order to improve the test time sufficiently.
In addition, since the prior art memory arrangement has a multi-bit data terminal for receiving an address selection signal, an additional signal switching circuit is required which can switch from an address selection signal to a data output signal at a high speed to input it to the memory circuit when a memory testing apparatus performs a memory reading test. This results in a complicated testing method.
Furthermore, since the multi-bit data input/output terminal shares the address selection input terminal, the parasitic capacitance at the input terminal is increased and results in a delayed addressing time.